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# Component - eth_dma ## Summary | Name | Location | Description | | --- | --- | --- | |eth_dma|mlite_pack.vhd#409|| ## Generics Count: 0 ## Ports Count: 21 | Name | Mode | Type | Description | | --- | --- | --- | --- | |clk|in|std_logic|| |reset|in|std_logic|| |enable_eth|in|std_logic|| |select_eth|in|std_logic|| |rec_isr|out|std_logic|| |send_isr|out|std_logic|| |address|out|std_logic_vector ( 31 downto 2 )|| |byte_we|out|std_logic_vector ( 3 downto 0 )|| |data_write|out|std_logic_vector ( 31 downto 0 )|| |data_read|in|std_logic_vector ( 31 downto 0 )|| |pause_in|in|std_logic|| |mem_address|in|std_logic_vector ( 31 downto 2 )|| |mem_byte_we|in|std_logic_vector ( 3 downto 0 )|| |data_w|in|std_logic_vector ( 31 downto 0 )|| |pause_out|out|std_logic|| |E_RX_CLK|in|std_logic|| |E_RX_DV|in|std_logic|| |E_RXD|in|std_logic_vector ( 3 downto 0 )|| |E_TX_CLK|in|std_logic|| |E_TX_EN|out|std_logic|| |E_TXD|out|std_logic_vector ( 3 downto 0 )||
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