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# Component - ddr_ctrl ## Summary | Name | Location | Description | | --- | --- | --- | |ddr_ctrl|mlite_pack.vhd#458|| ## Generics Count: 0 ## Ports Count: 25 | Name | Mode | Type | Description | | --- | --- | --- | --- | |clk|in|std_logic|| |clk_2x|in|std_logic|| |reset_in|in|std_logic|| |address|in|std_logic_vector ( 25 downto 2 )|| |byte_we|in|std_logic_vector ( 3 downto 0 )|| |data_w|in|std_logic_vector ( 31 downto 0 )|| |data_r|out|std_logic_vector ( 31 downto 0 )|| |active|in|std_logic|| |no_start|in|std_logic|| |no_stop|in|std_logic|| |pause|out|std_logic|| |SD_CK_P|out|std_logic|| |SD_CK_N|out|std_logic|| |SD_CKE|out|std_logic|| |SD_BA|out|std_logic_vector ( 1 downto 0 )|| |SD_A|out|std_logic_vector ( 12 downto 0 )|| |SD_CS|out|std_logic|| |SD_RAS|out|std_logic|| |SD_CAS|out|std_logic|| |SD_WE|out|std_logic|| |SD_DQ|inout|std_logic_vector ( 15 downto 0 )|| |SD_UDM|out|std_logic|| |SD_UDQS|inout|std_logic|| |SD_LDM|out|std_logic|| |SD_LDQS|inout|std_logic||
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