```{raw} html ``` # 674892be-d660-49a5-8871-e8a3492aa9cf ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| VHDL1014 | Split this process to only keep one clock. Clock signals: CLK_50MHZ, clk_reg | 20min | MEDIUM | - | - |