VHDL1014: Processes should only use one clock signal

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Adaptability \| Focused	20min	synthesis, bug-finder, clock, linty-ultra

Description

Noncompliant code example

process (clk1, clk2) is -- Noncompliant: Two clocks
begin
  if rising_edge(clk1) then
    s <= not s;
  end if;
  if rising_edge(clk2) then
    s <= s;
  end if;
end process;

Compliant solution

process (clk) is -- Compliant: One single clock
begin
  if rising_edge(clk) then
    s <= not s;
  end if;
end process;

An issue is raised when multiple clocks are used within the same process.

Parameters

No parameters.