```{raw} html ``` # d11e47b6-6a17-454b-9949-0cd87f315b05 ## Summary ```{raw} html
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| VHDL026 | Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types. | 20min | HIGH | - | - |