VHDL026: Only allowed port types should be used

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	20min	synthesis, linter, cnes, cnes-std-03400, cnes-std-03500

Description

Noncompliant code example

With the default values of allowed types:

Top-level entity: std_logic,std_logic_vector
Low-level entity/Component: std_logic,std_logic_vector

entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7);
    c : out integer -- Noncompliant: 'integer' is not part of the allowed types
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer; -- Noncompliant: 'integer' is not part of the allowed types
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer; -- Noncompliant: 'integer' is not part of the allowed types
  );
end component;

Compliant solution

With the default values of allowed types:

Top-level entity: std_logic,std_logic_vector
Low-level entity/Component: std_logic,std_logic_vector

entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7)
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7)
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
  );
end component;

With custom values of allowed types:

Top-level entity: std_logic,std_logic_vector
Low-level entity/Component: std_logic,std_logic_vector,integer

entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7)
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer
  );
end component;

Top-level entity ports are mapped on real component pins. Restrictions should apply to be sure that these VHDL pins map flawlessly to real pins. Thus, only use the following allowed types:

std_logic
std_logic_vector

Low-level entity/component port types are restricted to the following types:

std_logic
std_logic_vector

subtypes of those types, records of those types and arrays of those types.

Note that the list of allowed port types can be customized through parameters.

Parameters

Parameter	Value	Description

topLevelEntityAllowedTypes	std_logic,std_logic_vector	Comma separated list of allowed port types for top-level entities.
lowLevelEntityComponentAllowedTypes	std_logic,std_logic_vector	Comma separated list of allowed port types for low-level entities/components.