Back to Design Hierarchy Report
# Entity - bus_mux ## Summary | Name | Location | Description | | --- | --- | --- | |bus_mux|bus_mux.vhd#22|| ## Instantiations Count: 1 | Name | Location | Description | Details | | --- | --- | --- | :---: | | u5_bus_mux | mlite_cpu.vhd#249 | | | ## Generics Count: 0 ## Ports Count: 15 | Name | Mode | Type | Description | | --- | --- | --- | --- | |imm_in|in|std_logic_vector ( 15 downto 0 )|| |reg_source|in|std_logic_vector ( 31 downto 0 )|| |a_mux|in|a_source_type|| |a_out|out|std_logic_vector ( 31 downto 0 )|| |reg_target|in|std_logic_vector ( 31 downto 0 )|| |b_mux|in|b_source_type|| |b_out|out|std_logic_vector ( 31 downto 0 )|| |c_bus|in|std_logic_vector ( 31 downto 0 )|| |c_memory|in|std_logic_vector ( 31 downto 0 )|| |c_pc|in|std_logic_vector ( 31 downto 2 )|| |c_pc_plus4|in|std_logic_vector ( 31 downto 2 )|| |c_mux|in|c_source_type|| |reg_dest_out|out|std_logic_vector ( 31 downto 0 )|| |branch_func|in|branch_function_type|| |take_branch|out|std_logic||
Back to Design Hierarchy Report