Linty HDL Designer (HTML Report)
1
Summary Report
Design Hierarchy
Clock Domains
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Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
Linty HDL Designer (HTML Report)
1
Instantiation - u5_bus_mux
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Instantiation - u5_bus_mux
Summary
Name
Architecture
Description
u5_bus_mux
logic
Generics
Count: 0
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