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# FSM #1: state_reg
## Summary
|Name|Location|Graph|Reset State|States|Input Signals|Output Signals|
|---|---|:---:|---|---|---:|---:|
state_reg|cache.vhd#43|
|00| Count: 4
00
01
10
11|6|5||
## Input Signals
Count: 6
|Name|Declaration|
|---|---|
|address_next|cache.vhd#26|
|byte_we_next|cache.vhd#27|
|cache_tag_out|cache.vhd#50|
|cache_tag_reg|cache.vhd#49|
|mem_busy|cache.vhd#29|
|state|cache.vhd#44||
## Output Signals
Count: 5
|Name|Declaration|
|---|---|
|cache_checking|cache.vhd#32|
|cache_miss|cache.vhd#33|
|cache_tag_reg|cache.vhd#49|
|state|cache.vhd#44|
|state_next|cache.vhd#45|
## Transition table
|From|To|Input Control Signals|
|---|---|---|
|00|00|address_next: cache.vhd#26|
|00|01|address_next: cache.vhd#26
byte_we_next: cache.vhd#27|
|00|11|address_next: cache.vhd#26
byte_we_next: cache.vhd#27|
|01|00|address_next: cache.vhd#26
state: cache.vhd#44|
|01|00|cache_tag_out: cache.vhd#50
cache_tag_reg: cache.vhd#49
state: cache.vhd#44|
|01|01|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|01|10|cache_tag_out: cache.vhd#50
cache_tag_reg: cache.vhd#49
state: cache.vhd#44|
|01|11|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|10|00|address_next: cache.vhd#26
state: cache.vhd#44|
|10|01|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|10|10|mem_busy: cache.vhd#29
state: cache.vhd#44|
|10|11|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|10|11|mem_busy: cache.vhd#29
state: cache.vhd#44|
|11|00|address_next: cache.vhd#26
state: cache.vhd#44|
|11|00|mem_busy: cache.vhd#29
state: cache.vhd#44|
|11|01|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|11|11|address_next: cache.vhd#26
byte_we_next: cache.vhd#27
state: cache.vhd#44|
|11|11|mem_busy: cache.vhd#29
state: cache.vhd#44|
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