Finite State Machines (FSM)

Count: 2

Graph	Name	Location	Reset State	States	Unreachable States	Deadlock States	Livelock States	Input Signals	Output Signals	Details
	state_prev	ddr_ctrl.vhd#114	4’0000	Count: 9 4’0000 4’0001 4’0010 4’0011 4’0100 4’0101 4’0110 4’0111 4’1000	Count: 0	Count:  0	Count: 0	10	6	Details
	state_reg	cache.vhd#43	2’00	Count: 4 2’00 2’01 2’10 2’11	Count: 0	Count:  0	Count: 0	6	5	Details