# Summary Report |Report|Summary|Details| |---|---|:---:| |**Design Hierarchy**|Modules: 15
Instantiations: 15|View Details| |**Clock Domains**|Clock domains: 3|View Details| |**Reset Domains**|Global reset domains: 2|View Details| |**Clock Domain Crossings (CDC)**|CDCs: 33|View Details| |**Reset Domain Crossings (RDC)**|RDCs: 0|View Details| |**Finite State Machines (FSM)**|FSMs: 2|View Details| |**Combinational Loops**|Loops: 0|View Details| |**Latches**|Latches: 0|View Details|