# Summary Report
|Report|Summary|Details|
|---|---|:---:|
|**Design Hierarchy**|Modules: 15
Instantiations: 15|
|
|**Clock Domains**|Clock domains: 3|
|
|**Reset Domains**|Global reset domains: 2|
|
|**Clock Domain Crossings (CDC)**|CDCs: 33|
|
|**Reset Domain Crossings (RDC)**|RDCs: 0|
|
|**Finite State Machines (FSM)**|FSMs: 2|
|
|**Combinational Loops**|Loops: 0|
|
|**Latches**|Latches: 0|
|