Reset Domains

Global Reset Domains

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Count: 2

Name: Origin	Asynchronous	Synchronous	Active High	Active Low	Clock Domain(s)	Graph	Details
ROT_CENTER   - ROT_CENTER: plasma_3e.vhd#73 (Port)	✔	✗	✔	✗		Graph	Details
Complex: u1_plama.u1_cpu.u1_pc_next.reset_in   - ROT_CENTER: plasma_3e.vhd#73 (Port)   - u1_plama.u1_cpu.reset_reg: mlite_cpu.vhd#160 (Flip-flop)	✔	✗	✔	✗	- clk_reg (rising)	Graph	Details

Local Reset Domains

Count: 0

Reset Management Module (RMM)

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mlite_cpu instantiated as u1_cpu