Summary Report
Report |
Summary |
Details |
|---|---|---|
Design Hierarchy |
Modules: 15 |
|
Clock Domains |
Clock domains: 3 |
|
Reset Domains |
Global reset domains: 2 |
|
Clock Domain Crossings (CDC) |
CDCs: 33 |
|
Reset Domain Crossings (RDC) |
RDCs: 0 |
|
Unsynchronized Async Reset Release |
Unsynchronized releases: 51 |
|
Finite State Machines (FSM) |
FSMs: 2 |
|
Combinational Loops |
Loops: 0 |
|
Latches |
Latches: 0 |
|
Custom Graphs |
Custom graphs: 2 |
|
Quality Profiles |
VHDL: Deep Code Checks (108) |
|
Coding Quality |
Opened Issues: 832 |