Linty HDL Designer (HTML Report)

v1.2.3
  • Summary Report
  • Design Hierarchy
    • Summary
    • Dependencies
    • VHDL Entities
    • VHDL Packages
  • Clock Domains
    • Clock Domains
    • Clock Management Module (CMM)
  • Reset Domains
    • Global Reset Domains
    • Local Reset Domains
    • Reset Management Module (RMM)
  • Clock Domain Crossings (CDC)
  • Reset Domain Crossings (RDC)
  • Unsynchronized Async Reset Release
  • Finite State Machines (FSM)
  • Combinational Loops
  • Latches
  • Custom Graphs
  • Quality Profiles
    • VHDL
    • Verilog / SystemVerilog
    • HDL
  • Coding Quality
    • Measures
    • Opened Issues
      • VHDL
      • Verilog / SystemVerilog
      • HDL
    • Accepted Issues
      • VHDL
      • Verilog / SystemVerilog
      • HDL
    • False-Positive Issues
      • VHDL
      • Verilog / SystemVerilog
      • HDL
Linty HDL Designer (HTML Report)

v1.2.3
  • Linty Report
  • View page source

Linty Report

  • Summary Report
  • Design Hierarchy
  • Clock Domains
  • Reset Domains
  • Clock Domain Crossings (CDC)
  • Reset Domain Crossings (RDC)
  • Unsynchronized Async Reset Release
  • Finite State Machines (FSM)
  • Combinational Loops
  • Latches
  • Custom Graphs
  • Quality Profiles
  • Coding Quality
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Linty HDL Designer (HTML Report) · v1.2.3

Generated October 13, 2026 at 08:30:03 by Linty (7.8.0-SNAPSHOT)