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clk_reg (rising) => CLK_50MHZ (falling)

Origin Clock Domain	Target Clock Domain	Number of CDCs	Graph
clk_reg (rising)	CLK_50MHZ (falling)	6

CDCs

Summary

ID	Graph	Origin Signal	Target Signal	Details
7		u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg	u2_ddr.byte_we_reg2
26		u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg	u2_ddr.data_write2
27		u1_plama.u1_cpu.intr_signal	u2_ddr.data_write2
29		u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg	u2_ddr.data_write2
30		u1_plama.u1_cpu.intr_signal	u2_ddr.data_write2
31		u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg	u2_ddr.byte_we_reg2

CDC #7

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg Usage: - mem_ctrl.vhd#170 - mem_ctrl.vhd#174	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.byte_we_reg2 Usage: - ddr_ctrl.vhd#287 - ddr_ctrl.vhd#294 - ddr_ctrl.vhd#297	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

CDC #26

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg Usage: - mem_ctrl.vhd#167 - mem_ctrl.vhd#168 - mem_ctrl.vhd#176 - mem_ctrl.vhd#178	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.data_write2 Usage: - ddr_ctrl.vhd#286 - ddr_ctrl.vhd#293 - ddr_ctrl.vhd#296	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

CDC #27

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.intr_signal Usage: - mlite_cpu.vhd#162 - mlite_cpu.vhd#173 - mlite_cpu.vhd#175	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > mlite_cpu.vhd#160

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.data_write2 Usage: - ddr_ctrl.vhd#286 - ddr_ctrl.vhd#293 - ddr_ctrl.vhd#296	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

CDC #29

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg Usage: - mem_ctrl.vhd#167 - mem_ctrl.vhd#168 - mem_ctrl.vhd#176 - mem_ctrl.vhd#178	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.data_write2 Usage: - ddr_ctrl.vhd#286 - ddr_ctrl.vhd#293 - ddr_ctrl.vhd#296	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

CDC #30

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.intr_signal Usage: - mlite_cpu.vhd#162 - mlite_cpu.vhd#173 - mlite_cpu.vhd#175	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > mlite_cpu.vhd#160

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.data_write2 Usage: - ddr_ctrl.vhd#286 - ddr_ctrl.vhd#293 - ddr_ctrl.vhd#296	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

CDC #31

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg Usage: - mem_ctrl.vhd#170 - mem_ctrl.vhd#174	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: u2_ddr.byte_we_reg2 Usage: - ddr_ctrl.vhd#287 - ddr_ctrl.vhd#294 - ddr_ctrl.vhd#297	CLK_50MHZ (falling)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#284

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