Coding Quality

Measures

MeasureValue
Lines7,255
Files21
Lines of code6,034
Comments lines731

Opened Issues

Count: 832

LanguageIssues
VHDL710
Verilog / SystemVerilog0
HDL122
FileBlockerHighMediumLowInfo
alu.vhd08100
bus_mux.vhd00440
cache.vhd062951
control.vhd03710
ddr_ctrl.vhd06159121
eth_dma.vhd035130
mem_ctrl.vhd0171640
mlite_cpu.vhd0116110
mlite_pack.vhd0590360
mult.vhd0176130
pc_next.vhd05310
pipeline.vhd001610
plasma.vhd0101270
plasma_3e.vhd03412160
plasma_if.vhd06650
ram.vhd052220
ram_xilinx.vhd0110100
reg_bank.vhd0811120
shifter.vhd04180
tbench.vhd0143110
uart.vhd01942150
SeverityIssues
Blocker0
High291
Medium352
Low187
Info2

VHDL

Count: 710

RuleMessageLocationDetails
VHDL009Rename with different names.ram.vhd#23Details
VHDL025Replace by one of the following allowed port modes: in, outddr_ctrl.vhd#83Details
VHDL025Replace by one of the following allowed port modes: in, outddr_ctrl.vhd#85Details
VHDL025Replace by one of the following allowed port modes: in, outddr_ctrl.vhd#87Details
VHDL025Replace by one of the following allowed port modes: in, outplasma_if.vhd#25Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#168Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#169Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#170Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#171Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#172Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#173Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#174Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#175Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#176Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#177Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#178Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#179Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#180Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#188Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#189Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#190Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#191Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#192Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#193Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#194Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#195Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#196Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#197Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#198Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#199Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#200Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#201Details
VHDL026Replace by one of the following allowed port types: std_logic, std_logic_vector, subtype of those types, record of those types or array of those types.mlite_pack.vhd#202Details
VHDL029Add "range" constraint to this natural declaration.cache.vhd#165Details
VHDL029Add "range" constraint to this integer declaration.ddr_ctrl.vhd#139Details
VHDL029Add "range" constraint to this natural declaration.mlite_cpu.vhd#79Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#114Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#115Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#116Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#143Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#144Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#145Details
VHDL029Add "range" constraint to this natural declaration.mlite_pack.vhd#356Details
VHDL029Add "range" constraint to this natural declaration.ram.vhd#49Details
VHDL029Add "range" constraint to this integer declaration.ram_xilinx.vhd#47Details
VHDL029Add "range" constraint to this natural declaration.tbench.vhd#89Details
VHDL029Add "range" constraint to this natural declaration.uart.vhd#159Details
VHDL029Add "range" constraint to this natural declaration.uart.vhd#160Details
VHDL031Refactor this process to make it simpler to understand. Actual complexity (11) is greater than the maximum authorized complexity (10).cache.vhd#54Details
VHDL031Refactor this process to make it simpler to understand. Actual complexity (25) is greater than the maximum authorized complexity (10).ddr_ctrl.vhd#128Details
VHDL031Refactor this process to make it simpler to understand. Actual complexity (14) is greater than the maximum authorized complexity (10).eth_dma.vhd#69Details
VHDL031Refactor this process to make it simpler to understand. Actual complexity (15) is greater than the maximum authorized complexity (10).mem_ctrl.vhd#54Details
VHDL031Refactor this process to make it simpler to understand. Actual complexity (14) is greater than the maximum authorized complexity (10).uart.vhd#49Details
VHDL032Remove this signal initialization.tbench.vhd#31Details
VHDL032Remove this signal initialization.tbench.vhd#32Details
VHDL032Remove this signal initialization.tbench.vhd#33Details
VHDL032Remove this signal initialization.tbench.vhd#38Details
VHDL032Remove this signal initialization.tbench.vhd#39Details
VHDL032Remove this signal initialization.tbench.vhd#45Details
VHDL033This file has 479 lines of code, which is greater than 350 authorized. Split it into smaller files.mlite_pack.vhdDetails
VHDL033This file has 2,532 lines of code, which is greater than 350 authorized. Split it into smaller files.ram_xilinx.vhdDetails
VHDL126Move this declaration to a dedicated line.reg_bank.vhd#46Details
VHDL126Move this declaration to a dedicated line.reg_bank.vhd#48Details
VHDL126Move this declaration to a dedicated line.reg_bank.vhd#154Details
VHDL126Move this declaration to a dedicated line.reg_bank.vhd#155Details
VHDL126Move this declaration to a dedicated line.reg_bank.vhd#156Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#30Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#30Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#30Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#30Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#31Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#31Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#31Details
VHDL126Move this declaration to a dedicated line.shifter.vhd#31Details
VHDL127Remove the usage of this forbidden attribute.mlite_pack.vhd#526Details
VHDL127Remove the usage of this forbidden attribute.uart.vhd#166Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#65Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#70Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#73Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#79Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#81Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#87Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#89Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#94Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#98Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#103Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#106Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#111Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#114Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#121Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#125Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#127Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#131Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#132Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#134Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.cache.vhd#136Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#219Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#220Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#221Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#222Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#223Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#224Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#228Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#232Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#234Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#238Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#240Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#244Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#249Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#253Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#255Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#258Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#264Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#268Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#270Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#273Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#277Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#279Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#285Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#286Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#287Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#289Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#293Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#294Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#296Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#297Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#312Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#313Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#314Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#318Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#319Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.ddr_ctrl.vhd#320Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#79Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#80Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#81Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#82Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#83Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#84Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#85Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#86Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#87Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#88Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#89Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#93Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#97Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#98Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#100Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#101Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#108Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#109Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#110Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#111Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#113Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#118Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#122Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#123Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#124Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#126Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#129Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#131Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#137Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#138Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#140Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#143Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#144Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#145Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#147Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.eth_dma.vhd#149Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#166Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#167Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#168Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#169Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#170Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#173Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#174Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#175Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#176Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mem_ctrl.vhd#178Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mlite_cpu.vhd#161Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mlite_cpu.vhd#165Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#100Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#101Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#102Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#104Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#105Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#106Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#107Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#108Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#112Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#113Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#115Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#116Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#118Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#119Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#120Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#121Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#122Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#123Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#124Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#127Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#129Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#130Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#132Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#133Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#136Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#138Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#141Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#142Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#143Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#145Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#146Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#147Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#148Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#149Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#150Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#152Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#154Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#155Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#157Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#158Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#161Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#163Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#165Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#166Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#167Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#174Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#175Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#177Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#178Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#187Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#188Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#189Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#195Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#196Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#198Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#200Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#201Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#202Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.mult.vhd#204Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pc_next.vhd#60Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pc_next.vhd#63Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#90Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#92Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#102Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#103Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#104Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#105Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#125Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#126Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#127Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#131Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.pipeline.vhd#133Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#209Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#210Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#211Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#216Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#218Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#220Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma.vhd#224Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_3e.vhd#164Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_3e.vhd#166Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_3e.vhd#252Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_3e.vhd#256Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_3e.vhd#265Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_if.vhd#74Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.plasma_if.vhd#76Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.reg_bank.vhd#90Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.reg_bank.vhd#93Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.reg_bank.vhd#95Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#61Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#64Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#65Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#66Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#67Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#68Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#69Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#70Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#71Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#77Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#78Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#79Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#83Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#85Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#86Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#87Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#94Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#98Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#106Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#107Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#110Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#111Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#112Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#115Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#123Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#126Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#128Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#132Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#133Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#142Details
VHDL132Do not assign this signal that is listed in the process' sensitivity list.uart.vhd#144Details
VHDL134Remove this unused declaration.ddr_ctrl.vhd#94Details
VHDL134Remove this unused declaration.ddr_ctrl.vhd#100Details
VHDL134Remove this unused declaration.tbench.vhd#34Details
VHDL156Align component and related entity port names. Ports only defined in entity: no_ddr_start, no_ddr_stop.plasma_if.vhd#45Details
VHDL164Use 'TO' range direction instead.ddr_ctrl.vhd#136Details
VHDL164Use 'TO' range direction instead.reg_bank.vhd#43Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.ddr_ctrl.vhd#182Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.ddr_ctrl.vhd#187Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.eth_dma.vhd#96Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.eth_dma.vhd#121Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.eth_dma.vhd#139Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.mult.vhd#171Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.mult.vhd#173Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.mult.vhd#193Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.plasma.vhd#215Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.uart.vhd#105Details
VHDL172Refactor this code to not nest more than 2 conditional branching statements.uart.vhd#127Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#48Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#48Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#50Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#51Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#52Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#52Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#53Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#53Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#55Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#56Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#57Details
VHDL183Remove this usage of non-synthesizable statement.tbench.vhd#58Details
VHDL183Remove this usage of non-synthesizable statement.uart.vhd#156Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#182Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#182Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#195Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#195Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#217Details
VHDL185Update this reserved word to only use lowercase characters.mlite_cpu.vhd#217Details
VHDL185Update this reserved word to only use lowercase characters.mlite_pack.vhd#112Details
VHDL185Update this reserved word to only use lowercase characters.mlite_pack.vhd#138Details
VHDL185Update this reserved word to only use lowercase characters.mlite_pack.vhd#138Details
VHDL185Update this reserved word to only use lowercase characters.plasma.vhd#128Details
VHDL185Update this reserved word to only use lowercase characters.plasma.vhd#128Details
VHDL185Update this reserved word to only use lowercase characters.plasma.vhd#153Details
VHDL185Update this reserved word to only use lowercase characters.plasma.vhd#153Details
VHDL185Update this reserved word to only use lowercase characters.plasma_3e.vhd#198Details
VHDL185Update this reserved word to only use lowercase characters.plasma_3e.vhd#198Details
VHDL185Update this reserved word to only use lowercase characters.plasma_if.vhd#136Details
VHDL185Update this reserved word to only use lowercase characters.plasma_if.vhd#136Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#100Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#100Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#110Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#110Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#118Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#118Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#128Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#128Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#136Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#136Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#146Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#146Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#154Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#154Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#164Details
VHDL185Update this reserved word to only use lowercase characters.ram.vhd#164Details
VHDL185Update this reserved word to only use lowercase characters.ram_xilinx.vhd#58Details
VHDL185Update this reserved word to only use lowercase characters.ram_xilinx.vhd#58Details
VHDL185Update this reserved word to only use lowercase characters.ram_xilinx.vhd#58Details
VHDL185Update this reserved word to only use lowercase characters.ram_xilinx.vhd#58Details
VHDL185Update this reserved word to only use lowercase characters.tbench.vhd#65Details
VHDL185Update this reserved word to only use lowercase characters.tbench.vhd#65Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#112Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#141Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#164Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#184Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#205Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#218Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#241Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#260Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#274Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#295Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#303Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#311Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#321Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#351Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#371Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#385Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#395Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#409Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#436Details
VHDL193Replace component declaration and instantiation by a direct instantiation.mlite_pack.vhd#458Details
VHDL193Replace component declaration and instantiation by a direct instantiation.plasma_3e.vhd#86Details
VHDL193Replace component declaration and instantiation by a direct instantiation.plasma_3e.vhd#108Details
VHDL193Replace component declaration and instantiation by a direct instantiation.plasma_if.vhd#42Details
VHDL211Remove the usage of this Synopsys library.cache.vhd#16Details
VHDL211Remove the usage of this Synopsys library.ddr_ctrl.vhd#53Details
VHDL211Remove the usage of this Synopsys library.ddr_ctrl.vhd#54Details
VHDL211Remove the usage of this Synopsys library.eth_dma.vhd#18Details
VHDL211Remove the usage of this Synopsys library.eth_dma.vhd#19Details
VHDL211Remove the usage of this Synopsys library.mlite_cpu.vhd#72Details
VHDL211Remove the usage of this Synopsys library.mult.vhd#41Details
VHDL211Remove the usage of this Synopsys library.mult.vhd#42Details
VHDL211Remove the usage of this Synopsys library.plasma_3e.vhd#15Details
VHDL211Remove the usage of this Synopsys library.plasma_3e.vhd#16Details
VHDL211Remove the usage of this Synopsys library.ram.vhd#17Details
VHDL211Remove the usage of this Synopsys library.ram.vhd#18Details
VHDL211Remove the usage of this Synopsys library.ram_xilinx.vhd#38Details
VHDL211Remove the usage of this Synopsys library.reg_bank.vhd#15Details
VHDL211Remove the usage of this Synopsys library.tbench.vhd#15Details
VHDL211Remove the usage of this Synopsys library.uart.vhd#15Details
VHDL211Remove the usage of this Synopsys library.uart.vhd#17Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#24Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#25Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#26Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#54Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#69Details
VHDL212Rename this port to not include pin number.plasma_3e.vhd#70Details
VHDL213Add an end label.bus_mux.vhd#59Details
VHDL213Add an end label.bus_mux.vhd#86Details
VHDL213Add an end label.bus_mux.vhd#105Details
VHDL213Add an end label.bus_mux.vhd#134Details
VHDL213Add an end label.cache.vhd#140Details
VHDL213Add an end label.cache.vhd#174Details
VHDL213Add an end label.control.vhd#479Details
VHDL213Add an end label.ddr_ctrl.vhd#351Details
VHDL213Add an end label.eth_dma.vhd#181Details
VHDL213Add an end label.mem_ctrl.vhd#194Details
VHDL213Add an end label.mlite_cpu.vhd#180Details
VHDL213Add an end label.mult.vhd#211Details
VHDL213Add an end label.pc_next.vhd#69Details
VHDL213Add an end label.pipeline.vhd#137Details
VHDL213Add an end label.plasma.vhd#226Details
VHDL213Add an end label.plasma.vhd#254Details
VHDL213Add an end label.plasma_3e.vhd#168Details
VHDL213Add an end label.plasma_3e.vhd#274Details
VHDL213Add an end label.plasma_if.vhd#86Details
VHDL213Add an end label.plasma_if.vhd#131Details
VHDL213Add an end label.ram.vhd#90Details
VHDL213Add an end label.ram_xilinx.vhd#91Details
VHDL213Add an end label.ram_xilinx.vhd#96Details
VHDL213Add an end label.reg_bank.vhd#100Details
VHDL213Add an end label.reg_bank.vhd#123Details
VHDL213Add an end label.reg_bank.vhd#144Details
VHDL213Add an end label.reg_bank.vhd#315Details
VHDL213Add an end label.tbench.vhd#116Details
VHDL213Add an end label.uart.vhd#150Details
VHDL213Add an end label.uart.vhd#177Details
VHDL217Update design to split this case statement. Actual number of "when" clauses: 28. Maximum number of allowed "when" clauses: 16.control.vhd#83Details
VHDL217Update design to split this case statement. Actual number of "when" clauses: 30. Maximum number of allowed "when" clauses: 16.control.vhd#85Details
VHDL222Remove this forbidden pragma.mlite_pack.vhd#165Details
VHDL222Remove this forbidden pragma.mlite_pack.vhd#167Details
VHDL222Remove this forbidden pragma.mlite_pack.vhd#185Details
VHDL222Remove this forbidden pragma.mlite_pack.vhd#187Details
VHDL222Remove this forbidden pragma.uart.vhd#152Details
VHDL222Remove this forbidden pragma.uart.vhd#179Details
VHDL224Remove this internal tristate.alu.vhd#48Details
VHDL224Remove this internal tristate.alu.vhd#50Details
VHDL224Remove this internal tristate.alu.vhd#51Details
VHDL224Remove this internal tristate.alu.vhd#52Details
VHDL224Remove this internal tristate.alu.vhd#53Details
VHDL224Remove this internal tristate.alu.vhd#54Details
VHDL224Remove this internal tristate.alu.vhd#55Details
VHDL224Remove this internal tristate.ddr_ctrl.vhd#318Details
VHDL224Remove this internal tristate.ddr_ctrl.vhd#319Details
VHDL224Remove this internal tristate.ddr_ctrl.vhd#320Details
VHDL224Remove this internal tristate.ddr_ctrl.vhd#321Details
VHDL224Remove this internal tristate.ddr_ctrl.vhd#322Details
VHDL224Remove this internal tristate.plasma_if.vhd#100Details
VHDL224Remove this internal tristate.plasma_if.vhd#109Details
VHDL224Remove this internal tristate.plasma_if.vhd#121Details
VHDL224Remove this internal tristate.shifter.vhd#58Details
VHDL224Remove this internal tristate.shifter.vhd#60Details
VHDL224Remove this internal tristate.shifter.vhd#61Details
VHDL227This process has 306 lines of code, which is greater than 100 authorized. Split it into smaller processes.control.vhd#49Details
VHDL227This process has 160 lines of code, which is greater than 100 authorized. Split it into smaller processes.ddr_ctrl.vhd#128Details
VHDL227This process has 113 lines of code, which is greater than 100 authorized. Split it into smaller processes.mem_ctrl.vhd#54Details
VHDL236Use "OTHERS => '1'" instead.bus_mux.vhd#73Details
VHDL236Use "OTHERS => '0'" instead.bus_mux.vhd#78Details
VHDL236Use "OTHERS => '1'" instead.bus_mux.vhd#80Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#224Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#249Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#264Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#268Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#285Details
VHDL236Use "OTHERS => '0'" instead.ddr_ctrl.vhd#287Details
VHDL236Use "OTHERS => 'Z'" instead.ddr_ctrl.vhd#320Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#79Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#80Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#82Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#84Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#85Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#88Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#108Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#137Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#143Details
VHDL236Use "OTHERS => '1'" instead.eth_dma.vhd#166Details
VHDL236Use "OTHERS => '0'" instead.eth_dma.vhd#171Details
VHDL236Use "OTHERS => '0'" instead.mem_ctrl.vhd#170Details
VHDL236Use "OTHERS => '0'" instead.mlite_cpu.vhd#161Details
VHDL236Use "OTHERS => '0'" instead.mult.vhd#104Details
VHDL236Use "OTHERS => '0'" instead.pipeline.vhd#103Details
VHDL236Use "OTHERS => '0'" instead.pipeline.vhd#104Details
VHDL236Use "OTHERS => '1'" instead.plasma.vhd#240Details
VHDL236Use "OTHERS => '0'" instead.plasma_3e.vhd#252Details
VHDL236Use "OTHERS => '0'" instead.plasma_3e.vhd#256Details
VHDL236Use "OTHERS => '0'" instead.reg_bank.vhd#58Details
VHDL236Use "OTHERS => '0'" instead.reg_bank.vhd#84Details
VHDL236Use "OTHERS => '0'" instead.uart.vhd#65Details
VHDL236Use "OTHERS => '0'" instead.uart.vhd#69Details
VHDL240Update design to split this case statement. Actual number of cases: 28. Maximum number of allowed cases: 16.control.vhd#83Details
VHDL240Update design to split this case statement. Actual number of cases: 30. Maximum number of allowed cases: 16.control.vhd#85Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.alu.vhd#17Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.cache.vhd#22Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_cpu.vhd#75Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_cpu.vhd#76Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_cpu.vhd#77Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_cpu.vhd#78Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#117Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#118Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#119Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#120Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#121Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#122Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#123Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#124Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#125Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#126Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#146Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#147Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#148Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#149Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#150Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#151Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#152Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#153Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#261Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#296Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#304Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#312Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#352Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#353Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#354Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#355Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#372Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#386Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#396Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#437Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mlite_pack.vhd#438Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.mult.vhd#46Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma.vhd#40Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma.vhd#41Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_3e.vhd#20Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_3e.vhd#21Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_3e.vhd#87Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_3e.vhd#88Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_if.vhd#43Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.plasma_if.vhd#44Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.ram.vhd#24Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.ram_xilinx.vhd#45Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.reg_bank.vhd#21Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.shifter.vhd#18Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.tbench.vhd#21Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.tbench.vhd#27Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, boolean, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.uart.vhd#22Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.uart.vhd#157Details
VHDL303Replace by one of the following allowed types: bit, bit_vector, integer, natural, positive, signed, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, unsigned, any enumerated type, subtype of those types, record of those types or array of those types.uart.vhd#158Details
VHDL306Keep only one single architecture for this entity.ram.vhd#23Details
VHDL306Keep only one single architecture for this entity.ram_xilinx.vhd#44Details
VHDL315Implement this empty conditional branch or remove it.control.vhd#210Details
VHDL315Implement this empty conditional branch or remove it.control.vhd#243Details
VHDL315Implement this empty conditional branch or remove it.control.vhd#440Details
VHDL315Implement this empty conditional branch or remove it.mem_ctrl.vhd#131Details
VHDL316Too many ports. Actual: 15. Allowed: 6. Split this entity into single-responsibility entities.bus_mux.vhd#22Details
VHDL316Too many ports. Actual: 9. Allowed: 6. Split this entity into single-responsibility entities.cache.vhd#21Details
VHDL316Too many ports. Actual: 16. Allowed: 6. Split this entity into single-responsibility entities.control.vhd#27Details
VHDL316Too many ports. Actual: 25. Allowed: 6. Split this entity into single-responsibility entities.ddr_ctrl.vhd#57Details
VHDL316Too many ports. Actual: 21. Allowed: 6. Split this entity into single-responsibility entities.eth_dma.vhd#22Details
VHDL316Too many ports. Actual: 17. Allowed: 6. Split this entity into single-responsibility entities.mem_ctrl.vhd#17Details
VHDL316Too many ports. Actual: 10. Allowed: 6. Split this entity into single-responsibility entities.mlite_cpu.vhd#74Details
VHDL316Too many ports. Actual: 7. Allowed: 6. Split this entity into single-responsibility entities.mult.vhd#45Details
VHDL316Too many ports. Actual: 10. Allowed: 6. Split this entity into single-responsibility entities.pc_next.vhd#16Details
VHDL316Too many ports. Actual: 26. Allowed: 6. Split this entity into single-responsibility entities.pipeline.vhd#18Details
VHDL316Too many ports. Actual: 13. Allowed: 6. Split this entity into single-responsibility entities.plasma.vhd#39Details
VHDL316Too many ports. Actual: 16. Allowed: 6. Split this entity into single-responsibility entities.plasma_if.vhd#18Details
VHDL316Too many ports. Actual: 10. Allowed: 6. Split this entity into single-responsibility entities.reg_bank.vhd#20Details
VHDL316Too many ports. Actual: 10. Allowed: 6. Split this entity into single-responsibility entities.uart.vhd#21Details
VHDL1005Update this FSM to use an enumerated type.cache.vhd#43Details
VHDL1005Update this FSM to use an enumerated type.ddr_ctrl.vhd#114Details
VHDL1012Remove this usage of the 'clk' clock signal.ddr_ctrl.vhd#273Details
VHDL1012Remove this usage of the 'clk_reg' clock signal.plasma_3e.vhd#164Details
VHDL1012Remove this usage of the 'clk_reg' clock signal.plasma_3e.vhd#166Details
VHDL1012Remove this usage of the 'clk_reg' clock signal.plasma_3e.vhd#166Details
VHDL1014Split this process to only keep one clock. Clock signals: clk, clk_2xddr_ctrl.vhd#128Details
VHDL1014Split this process to only keep one clock. Clock signals: CLK_50MHZ, clk_regplasma_3e.vhd#161Details
VHDL1015Split this process to only keep one edge transition direction per clock.ddr_ctrl.vhd#128Details
VHDL1033Review this usage of the 'reset_in' reset signal.mlite_cpu.vhd#154Details
VHDL1033Review this usage of the 'ROT_CENTER' reset signal.plasma_3e.vhd#170Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.cache.vhd#130Details
VHDL1041Enable signal: clk, polarity(ies): active-lowddr_ctrl.vhd#59Details
VHDL1041Enable signal: reset_in, polarity(ies): active-lowddr_ctrl.vhd#61Details
VHDL1041Enable signal: active, polarity(ies): active-highddr_ctrl.vhd#67Details
VHDL1041This flip-flop defines a complex enable involving 5 signals.ddr_ctrl.vhd#218Details
VHDL1041This flip-flop defines a complex enable involving 4 signals.ddr_ctrl.vhd#218Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.ddr_ctrl.vhd#263Details
VHDL1041This flip-flop defines a complex enable involving 5 signals.ddr_ctrl.vhd#263Details
VHDL1041Enable signal: pause_in, polarity(ies): active-lowmem_ctrl.vhd#20Details
VHDL1041This flip-flop defines a complex enable involving 4 signals.mem_ctrl.vhd#165Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.mem_ctrl.vhd#165Details
VHDL1041Enable signal: pause_any, polarity(ies): active-lowmlite_cpu.vhd#136Details
VHDL1041This flip-flop defines a complex enable involving 1 signal.mlite_cpu.vhd#160Details
VHDL1041This flip-flop defines a complex enable involving 5 signals.plasma.vhd#208Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.plasma_3e.vhd#251Details
VHDL1041This flip-flop defines a complex enable involving 1 signal.reg_bank.vhd#89Details
VHDL1041This flip-flop defines a complex enable involving 3 signals.uart.vhd#63Details
VHDL1041This flip-flop defines a complex enable involving 4 signals.uart.vhd#63Details
VHDL1041This flip-flop defines a complex enable involving 3 signals.uart.vhd#63Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.uart.vhd#63Details
VHDL1041This flip-flop defines a complex enable involving 2 signals.uart.vhd#63Details
VHDL1041This flip-flop defines a complex enable involving 5 signals.uart.vhd#63Details
VHDL1046Remove this non-enable usage of the 'reset_in' enable signal.ddr_ctrl.vhd#128Details
VHDL1046Remove this non-enable usage of the 'clk' enable signal.ddr_ctrl.vhd#128Details
VHDL1046Remove this non-enable usage of the 'active' enable signal.ddr_ctrl.vhd#129Details
VHDL1046Remove this non-enable usage of the 'clk' enable signal.ddr_ctrl.vhd#267Details
VHDL1046Remove this non-enable usage of the 'clk' enable signal.ddr_ctrl.vhd#273Details
VHDL1046Remove this non-enable usage of the 'pause_in' enable signal.mem_ctrl.vhd#54Details
VHDL1046Remove this non-enable usage of the 'pause_in' enable signal.mem_ctrl.vhd#140Details
VHDL1046Remove this non-enable usage of the 'pause_in' enable signal.mem_ctrl.vhd#149Details
VHDL1046Remove this non-enable usage of the 'pause_any' enable signal.mlite_cpu.vhd#158Details
VHDL1047Remove this complex enable involving 2 signals.cache.vhd#130Details
VHDL1047Remove this complex enable involving 5 signals.ddr_ctrl.vhd#218Details
VHDL1047Remove this complex enable involving 4 signals.ddr_ctrl.vhd#218Details
VHDL1047Remove this complex enable involving 5 signals.ddr_ctrl.vhd#263Details
VHDL1047Remove this complex enable involving 2 signals.ddr_ctrl.vhd#263Details
VHDL1047Remove this complex enable involving 4 signals.mem_ctrl.vhd#165Details
VHDL1047Remove this complex enable involving 2 signals.mem_ctrl.vhd#165Details
VHDL1047Remove this complex enable involving 1 signals.mlite_cpu.vhd#160Details
VHDL1047Remove this complex enable involving 5 signals.plasma.vhd#208Details
VHDL1047Remove this complex enable involving 2 signals.plasma_3e.vhd#251Details
VHDL1047Remove this complex enable involving 1 signals.reg_bank.vhd#89Details
VHDL1047Remove this complex enable involving 3 signals.uart.vhd#63Details
VHDL1047Remove this complex enable involving 2 signals.uart.vhd#63Details
VHDL1047Remove this complex enable involving 4 signals.uart.vhd#63Details
VHDL1047Remove this complex enable involving 5 signals.uart.vhd#63Details
VHDL1047Remove this complex enable involving 2 signals.uart.vhd#63Details
VHDL1047Remove this complex enable involving 3 signals.uart.vhd#63Details
VHDL1050Check if this entity can be synthesized with different configurations. If not, remove it.eth_dma.vhd#22Details
VHDL1050Check if this entity can be synthesized with different configurations. If not, remove it.pipeline.vhd#18Details
VHDL1050Check if this entity can be synthesized with different configurations. If not, remove it.plasma_if.vhd#18Details
VHDL1050Check if this entity can be synthesized with different configurations. If not, remove it.ram_xilinx.vhd#44Details
VHDL1050Check if this entity can be synthesized with different configurations. If not, remove it.tbench.vhd#17Details
VHDL1051Check if this architecture can be synthesized with different configurations. If not, remove it.eth_dma.vhd#49Details
VHDL1051Check if this architecture can be synthesized with different configurations. If not, remove it.pipeline.vhd#48Details
VHDL1051Check if this architecture can be synthesized with different configurations. If not, remove it.plasma_if.vhd#40Details
VHDL1051Check if this architecture can be synthesized with different configurations. If not, remove it.ram_xilinx.vhd#56Details
VHDL1051Check if this architecture can be synthesized with different configurations. If not, remove it.tbench.vhd#20Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.alu.vhd#46Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.mlite_cpu.vhd#307Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.plasma.vhd#142Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.plasma.vhd#290Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram.vhd#94Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#99Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#416Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#734Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#1052Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#1370Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#1688Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#2006Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.ram_xilinx.vhd#2324Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.reg_bank.vhd#110Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.reg_bank.vhd#152Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.reg_bank.vhd#243Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.reg_bank.vhd#293Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.shifter.vhd#57Details
VHDL1052Check if every non-synthesized if/elsif/else generate block can be reached with different configurations. If not, remove them.uart.vhd#153Details
VHDL1053Check this signal that is used as both a reset and an enable: reset_inddr_ctrl.vhd#61Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.cache.vhd#24Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.cache.vhd#24Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.ddr_ctrl.vhd#59Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.ddr_ctrl.vhd#59Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.ddr_ctrl.vhd#60Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.mem_ctrl.vhd#18Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.mem_ctrl.vhd#18Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.mlite_cpu.vhd#80Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.mlite_cpu.vhd#80Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.mult.vhd#47Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.mult.vhd#47Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.pc_next.vhd#17Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.pc_next.vhd#17Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.plasma.vhd#44Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.plasma.vhd#44Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.plasma_3e.vhd#140Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.plasma_3e.vhd#140Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.ram.vhd#25Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.ram.vhd#25Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.reg_bank.vhd#22Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.reg_bank.vhd#22Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: ROT_CENTER.uart.vhd#23Details
VHDL1061Rename this clock signal to preserve its name across the design. Source signal name: CLK_50MHZ.uart.vhd#23Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.cache.vhd#25Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.ddr_ctrl.vhd#61Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.mem_ctrl.vhd#19Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ.mem_ctrl.vhd#19Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.mlite_cpu.vhd#81Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ.mult.vhd#48Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.mult.vhd#48Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ.pc_next.vhd#18Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.pc_next.vhd#18Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.plasma.vhd#45Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.reg_bank.vhd#23Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: CLK_50MHZ.reg_bank.vhd#23Details
VHDL1062Rename this reset signal to preserve its name across the design. Source signal name: ROT_CENTER.uart.vhd#24Details
VHDL1070Remove frequency information from this clock signal.plasma_3e.vhd#24Details

Verilog / SystemVerilog

Count: 0

HDL

Count: 122

RuleMessageLocationDetails
HDL1001Review clock domain crossing between 'u2_ddr.write_prev' (target) and 'u2_ddr.cycle_count2' (origin)ddr_ctrl.vhd#225Details
HDL1001Review clock domain crossing between 'u2_ddr.write_active' (target) and 'u2_ddr.cycle_count2' (origin)ddr_ctrl.vhd#225Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.address_reg' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.bank_open' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.data_read' (target) and 'u2_ddr.write_active' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.write_prev' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.bank_open' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.data_read' (target) and 'u2_ddr.write_active' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.state_prev' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u1_plama.opt_cache2.u_cache.state_reg' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.bank_open' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.refresh_cnt' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.data_read' (target) and 'u2_ddr.data_write2' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.data_read' (target) and 'u2_ddr.data_write2' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count' (target) and 'u2_ddr.bank_open' (origin)ddr_ctrl.vhd#265Details
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.byte_we_reg2' (target) and 'clk_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'clk_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.intr_signal' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.cycle_count2' (target) and 'u2_ddr.cycle_count' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.byte_we_reg2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.intr_signal' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.byte_we_reg2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (origin)ddr_ctrl.vhd#288Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (target) and 'u2_ddr.data_read' (origin)mem_ctrl.vhd#171Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg' (target) and 'u2_ddr.data_read' (origin)mem_ctrl.vhd#171Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg' (target) and 'u2_ddr.data_read' (origin)mem_ctrl.vhd#171Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (target) and 'u2_ddr.data_read' (origin)mem_ctrl.vhd#171Details
HDL1001Review clock domain crossing between 'u1_plama.u2_ram.generic_ram.ram_proc.data' (target) and 'u2_ddr.data_read' (origin)ram.vhd#65Details
HDL1001Review clock domain crossing between 'u1_plama.u2_ram.generic_ram.ram_proc.data' (target) and 'u2_ddr.data_read' (origin)ram.vhd#65Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg' (target) and 'u2_ddr.data_read' (origin)reg_bank.vhd#91Details
HDL1001Review clock domain crossing between 'u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg' (target) and 'u2_ddr.data_read' (origin)reg_bank.vhd#91Details
HDL1002Reduce the number of clock domains in this design. Maximum allowed number: 1. Actual number: 3.plasma_3e.vhd#19Details
HDL1005address_next(31:2) input port is partially unconnected. Unconnected bit offsets: 31. Update design to remove this unconnected input port.cache.vhd#26Details
HDL1005cpu_address(31:2) input port is partially unconnected. Unconnected bit offsets: 31:12. Update design to remove this unconnected input port.cache.vhd#28Details
HDL1005address(31:2) input port is partially unconnected. Unconnected bit offsets: 31:13. Update design to remove this unconnected input port.ram.vhd#28Details
HDL1008'SD_CK_N' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#29Details
HDL1008'SD_A(12:0)' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#33Details
HDL1008'SD_CS' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#34Details
HDL1008'SD_RAS' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#35Details
HDL1008'SD_CAS' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#36Details
HDL1008'SD_WE' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#37Details
HDL1008'SD_DQ(15:0)' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#39Details
HDL1008'SD_UDM' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#40Details
HDL1008'SD_UDQS' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#41Details
HDL1008'SD_LDM' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#42Details
HDL1008'SD_LDQS' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#43Details
HDL1008'E_MDIO' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#46Details
HDL1008'SF_CE0' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#54Details
HDL1008'SF_OE' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#55Details
HDL1008'SF_A(24:0)' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#59Details
HDL1008'SF_D(15:1)' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#60Details
HDL1008'SPI_MISO' output port is unregistered. Update design to remove combinational elements from this output signal path.plasma_3e.vhd#61Details
HDL1010E_TX_EN output port is constant. Update design to remove this constant output port.plasma_3e.vhd#51Details
HDL1010E_TXD(3:0) output port is constant. Update design to remove this constant output port.plasma_3e.vhd#52Details
HDL1010SF_BYTE output port is constant. Update design to remove this constant output port.plasma_3e.vhd#57Details
HDL1011Update design to remove direct connection between imm_out and opcode.control.vhd#33Details
HDL1011Update design to remove direct connection between SD_BA and address.ddr_ctrl.vhd#76Details
HDL1012Reduce the number of dependent modules. Actual: 8. Allowed: 4plasma.vhd#126Details
HDL1013All clocks should be generated within a unique clock management module.plasma_3e.vhd#19Details
HDL1023Finite state machine: state_reg (States: 4, Input signals: 6, Output signals: 5)cache.vhd#43Details
HDL1023Finite state machine: state_prev (States: 9, Input signals: 10, Output signals: 6)ddr_ctrl.vhd#114Details
HDL1026Simplify this FSM. Actual number of output signals: 5. Maximum allowed number of output signals: 2.cache.vhd#43Details
HDL1026Simplify this FSM. Actual number of output signals: 6. Maximum allowed number of output signals: 2.ddr_ctrl.vhd#114Details
HDL1027Simplify this FSM. Actual number of input signals: 6. Maximum allowed number of input signals: 2.cache.vhd#43Details
HDL1027Simplify this FSM. Actual number of input signals: 10. Maximum allowed number of input signals: 2.ddr_ctrl.vhd#114Details
HDL1029Decrease FSM complexity. From at least one state, a transition is possible to more than 2 other states.cache.vhd#43Details
HDL1029Decrease FSM complexity. From at least one state, a transition is possible to more than 2 other states.ddr_ctrl.vhd#114Details
HDL1045Decrease the number of clock domains used by this instance. Actual: 2. Max expected: 1.plasma_3e.vhd#84Details
HDL1045Decrease the number of clock domains used by this instance. Actual: 3. Max expected: 1.plasma_3e.vhd#215Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.cache.vhd#130Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.cache.vhd#130Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.ddr_ctrl.vhd#218Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#263Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#284Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#284Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#284Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#284Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.ddr_ctrl.vhd#284Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mem_ctrl.vhd#165Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mem_ctrl.vhd#165Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mem_ctrl.vhd#165Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mem_ctrl.vhd#165Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mem_ctrl.vhd#165Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mlite_cpu.vhd#160Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mlite_cpu.vhd#160Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.mult.vhd#99Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.pc_next.vhd#59Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.plasma.vhd#208Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.plasma.vhd#208Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.plasma.vhd#208Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops.plasma_3e.vhd#163Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.plasma_3e.vhd#251Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.plasma_3e.vhd#251Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.reg_bank.vhd#89Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details
HDL1051Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops.uart.vhd#63Details

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