Unsynchronized Async Reset Release

Count: 51

Required flip-flops in synchronizer: 2

Asynchronous resets released into a clock domain without a reset-release synchronizer of at least 2 flip-flops clocked by that domain:

Graph	Flip-flop	Asynchronous reset on clock domain	Destination clock
Graph	cache.vhd#130	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	cache.vhd#130	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#218	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	ddr_ctrl.vhd#263	u1_plama.reset	u2_ddr.clk_2x
Graph	ddr_ctrl.vhd#284	u1_plama.reset	u2_ddr.clk_2x
Graph	ddr_ctrl.vhd#284	u1_plama.reset	u2_ddr.clk_2x
Graph	ddr_ctrl.vhd#284	u1_plama.reset	u2_ddr.clk_2x
Graph	ddr_ctrl.vhd#284	u1_plama.reset	u2_ddr.clk_2x
Graph	ddr_ctrl.vhd#284	u1_plama.reset	u2_ddr.clk_2x
Graph	mem_ctrl.vhd#165	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mem_ctrl.vhd#165	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mem_ctrl.vhd#165	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mem_ctrl.vhd#165	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mem_ctrl.vhd#165	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mlite_cpu.vhd#160	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mlite_cpu.vhd#160	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	mult.vhd#99	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	pc_next.vhd#59	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	plasma.vhd#208	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	plasma.vhd#208	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	plasma.vhd#208	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	plasma_3e.vhd#163	u1_plama.reset	u2_ddr.clk_2x
Graph	plasma_3e.vhd#251	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	plasma_3e.vhd#251	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	reg_bank.vhd#89	u1_plama.u1_cpu.u4_reg_bank.reset_in	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk
Graph	uart.vhd#63	u1_plama.reset	u1_plama.u1_cpu.u4_reg_bank.clk