| VERILOG002 | "FIXME" tags should be handled | Details |
| VERILOG003 | Complete the task associated to this "TODO" comment | Details |
| VERILOG005 | Empty files should be removed | Details |
| VERILOG008 | Files should not have too many lines of code | Details |
| VERILOG022 | Branching preprocessor directives should be aligned to the left | Details |
| VERILOG023 | "default" case item should include a colon | Details |
| VERILOG025 | Program should not be used | Details |
| VERILOG026 | "logic" should be used instead of "reg" and "wire" | Details |
| VERILOG027 | "defparam" should not be used | Details |
| VERILOG028 | Each file should define one single design unit | Details |
| VERILOG029 | Each case statement should define a "default" case | Details |
| VERILOG031 | "default" should be the last item of a "case" statement | Details |
| VERILOG032 | Escaped identifiers should not be used | Details |
| VERILOG034 | Forbidden system tasks and functions should not be used | Details |
| VERILOG046 | Legacy generate regions should not be used | Details |
| VERILOG048 | "always_comb" should be used instead of "always @*" | Details |
| VERILOG051 | Begin/End identifiers/labels should match | Details |
| VERILOG052 | Functions and tasks declared outside of a class should have an explicit lifetime | Details |
| VERILOG054 | Functions should have an "automatic" lifetime to be used in synthesizable code | Details |
| VERILOG057 | Named parameters should be used for all instantiations and class parameter overrides | Details |
| VERILOG058 | Named port connections should be used for all instantiations | Details |
| VERILOG059 | .* should not be used as port connections of module/program/interface instantiations | Details |
| VERILOG075 | Deprecated separate "genvar" declarations should not be used | Details |
| VERILOG081 | Function and task arguments should have an explicit storage type | Details |
| VERILOG082 | "output", "inout" and "ref" directions should not be used in function arguments | Details |
| VERILOG083 | Default "input" direction should not be used in function arguments | Details |
| VERILOG096 | Empty ports should be removed from non-ANSI port lists | Details |
| VERILOG097 | Repeated ports should be removed from non-ANSI port lists | Details |
| VERILOG101 | Function return value should have an explicit storage type | Details |
| VERILOG2000 | Unused variables should be removed | Details |
| VERILOG2001 | Multiple defparam overrides targeting the same parameter should be removed | Details |
| VERILOG2002 | Unused task or function formal arguments should be removed | Details |
| VERILOG2003 | Unused assertion declarations (sequence, property or let) should be removed | Details |
| VERILOG2004 | Unused nets should be removed | Details |
| VERILOG2005 | An "inout" port that is never read should be converted into an "output" port | Details |
| VERILOG2006 | Unused configuration cell rules should be removed | Details |
| VERILOG2007 | Unused configuration instance rules should be removed | Details |
| VERILOG2008 | Unused modules / programs / interfaces should be removed | Details |
| VERILOG2009 | Unused genvar should be removed | Details |
| VERILOG2010 | Unused implicitly created nets should be removed | Details |
| VERILOG2011 | Unused package imports should be removed | Details |
| VERILOG2012 | Unused parameters should be removed | Details |
| VERILOG2013 | Unused input ports should be removed | Details |
| VERILOG2014 | An output port that is never given a value should be removed | Details |
| VERILOG2015 | Non-void function return values should not be ignored | Details |
| VERILOG2016 | Unused type parameters should be removed | Details |
| VERILOG2017 | Unused typedef should be removed | Details |
| VERILOG2018 | Unused wildcard package imports should be removed | Details |
| VERILOG2019 | Useless casts should be removed | Details |
| VERILOG2020 | Vectors should not overflow | Details |
| VERILOG2022 | An explicit cast should be added to implicit conversion that expands a type | Details |
| VERILOG2023 | Implicit conversions that truncate a type should be avoided | Details |
| VERILOG2024 | Arithmetic operators should have operands of same type | Details |
| VERILOG2025 | Procedurally force a bit-select or range select of a variable should not be used | Details |
| VERILOG2026 | Bitwise operators should have operands of same type | Details |
| VERILOG2027 | Duplicate case generate items should be removed | Details |
| VERILOG2028 | Add item to match case generate directive | Details |
| VERILOG2029 | Comparisons should have operands of same type | Details |
| VERILOG2030 | Implicit constant conversions that truncate should be fixed | Details |
| VERILOG2031 | Implicit class constraint blocks with no external definition should be removed | Details |
| VERILOG2032 | Deprecated "DPI" should be replaced by "DPI-C" | Details |
| VERILOG2033 | Pure "DPI" tasks should not be used | Details |
| VERILOG2034 | Duplicated attributes should be removed | Details |
| VERILOG2035 | Duplicated configuration rules should be removed | Details |
| VERILOG2036 | Duplicated package imports should be removed | Details |
| VERILOG2037 | Duplicated timing paths should be removed | Details |
| VERILOG2038 | Constant functions should not access nonexistent elements of dynamic arrays | Details |
| VERILOG2039 | Constant functions should not access nonexistent ranges of dynamic arrays | Details |
| VERILOG2040 | Constant functions should not access nonexistent elements of associative arrays | Details |
| VERILOG2041 | Bodies of conditional statements and loops should not be left empty | Details |
| VERILOG2042 | Useless semicolons in non-procedural scopes should be removed | Details |
| VERILOG2043 | Empty statements should be removed | Details |
| VERILOG2044 | Empty assignment pattern literals should not be used | Details |
| VERILOG2045 | Constant functions should not pop elements from empty queues | Details |
| VERILOG2046 | Enum members that are specified as ranges should only define ranges with integer literals | Details |
| VERILOG2047 | Event expressions should not be constant | Details |
| VERILOG2048 | Pragma protect keywords expecting string values should be set with string values | Details |
| VERILOG2049 | Pragma protect directives should not define unknown keywords | Details |
| VERILOG2050 | Pragma protect directives should define a keyword | Details |
| VERILOG2051 | "static" variables declared locally to a procedural block that contain an initializer should be explicitly defined with the "static" keyword | Details |
| VERILOG2052 | Pragma directives should define the right number of arguments | Details |
| VERILOG2053 | "pragma protect begin" directives should be properly paired with "pragma protect end" directives | Details |
| VERILOG2054 | The argument of the "$finish" control task should be a "finish number" of 0, 1, or 2 | Details |
| VERILOG2055 | Implicit conversion from a floating point value to a boolean value should be reviewed | Details |
| VERILOG2056 | Implicit conversion from a floating point value to an integer value should be reviewed | Details |
| VERILOG2057 | Implicit conversion from a floating point value to an narrower floating point value should be reviewed | Details |
| VERILOG2058 | Implicit conversion from a floating point value to an wider floating point value should be reviewed | Details |
| VERILOG2059 | Formatting multi-bit nets with the "%v" specifier should be avoided | Details |
| VERILOG2060 | Implicit conversions from real to integer value in string formatting function should be avoided | Details |
| VERILOG2061 | Implicit conversions between two unrelated types should be avoided | Details |
| VERILOG2062 | Out-of-bounds values used to index arrays should be fixed | Details |
| VERILOG2063 | Signing keywords with no effect should be removed | Details |
| VERILOG2064 | Implicit conversions from integer to boolean value should be reviewed | Details |
| VERILOG2065 | Implicit conversions from integer to real value should be reviewed | Details |
| VERILOG2066 | Integers should not overflow | Details |
| VERILOG2067 | Encoding bytes should be valid | Details |
| VERILOG2068 | Pragma protect keywords expecting integer values should be set with integer values | Details |
| VERILOG2069 | "pragma protect viewport" directive should be defined with valid options | Details |
| VERILOG2070 | Lifetime specifiers should not be used on method prototype declarations | Details |
| VERILOG2071 | String format specifiers should not be missing | Details |
| VERILOG2072 | Timing control edge expression should not be wider than one bit | Details |
| VERILOG2073 | System timing check parameters should always be positive | Details |
| VERILOG2074 | "pragma protect begin" directives should not be nested | Details |
| VERILOG2075 | Connections between external net and internal net port should have consistent net types | Details |
| VERILOG2076 | Nonblocking assignments should not be used in "final" blocks | Details |
| VERILOG2077 | "dist" constraint items should not be surrounded by parentheses | Details |
| VERILOG2078 | "\%" escape code should not be used | Details |
| VERILOG2079 | "foreach" loops should not use multidimensional brackets when declaring loop variables | Details |
| VERILOG2080 | Standalone "generate" blocks without a corresponding generate loop or condition should not be used | Details |
| VERILOG2081 | Useless void casts should be removed | Details |
| VERILOG2082 | Port direction should be set to "inout" when port is both read and written | Details |
| VERILOG2083 | Implicit conversions in port connection expressions should not expand types | Details |
| VERILOG2084 | Implicit conversions in port connection expressions should not truncate types | Details |
| VERILOG2085 | Pragma protect directives should not define unknown keyword options | Details |
| VERILOG2086 | Unsized types should not be used in concatenations | Details |
| VERILOG2087 | Pragma protect keywords expecting list of key/value options values should be set with list of key/value options values | Details |
| VERILOG2088 | Encoded block in protected envelope should not differ in size from what was specified in a prior encoding pragma directive | Details |
| VERILOG2089 | Out-of-bounds range should not be used to select from an array | Details |
| VERILOG2090 | An indexed part-select should not have a width that is wider than the bounds of the array it is selecting | Details |
| VERILOG2091 | Real literals should not be too large to be represented | Details |
| VERILOG2092 | Real literals should not be too small to be represented | Details |
| VERILOG2093 | Macros should not be redefined | Details |
| VERILOG2094 | An open range with constant bounds should not be reversed | Details |
| VERILOG2095 | Comparison operators should not have operands of differing signs | Details |
| VERILOG2096 | An implicit conversion should not change the signedness of an integer type | Details |
| VERILOG2097 | State-dependent path conditions in specify blocks should stick with the subset of expression types and operators defined by SystemVerilog standard | Details |
| VERILOG2098 | Parameters should not be used inside "specify" blocks | Details |
| VERILOG2099 | Dist weight operators (":=", ":/") should not be split | Details |
| VERILOG2100 | A static variable's initializer should not depend on another variable that does not have a defined order of initialization relative to the first | Details |
| VERILOG2101 | A static variable's initializer expression should not refer to uninitialized variables, nets, ports, or modport members | Details |
| VERILOG2102 | Constant functions should not contain static variables with initializer | Details |
| VERILOG2103 | Constant functions should not invoke tasks | Details |
| VERILOG2104 | Variables should be assigned a value before being used | Details |
| VERILOG2105 | Instance ports with no default value should not be left unconnected | Details |
| VERILOG2106 | Unnamed instance ports should not be left unconnected | Details |
| VERILOG2107 | A net that is used should have a value driven | Details |
| VERILOG2108 | Unknown character escape codes should not be used | Details |
| VERILOG2110 | Unknown pragma directives should be removed | Details |
| VERILOG2111 | Unknown pragma protect encoding should be fixed | Details |
| VERILOG2112 | An arithmetic right shift of an unsigned integral type should be avoided as it will always shift in zeros | Details |
| VERILOG2114 | "always_comb" or "always_ff" or "always_latch" should be used instead of "always" | Details |
| VERILOG2115 | "always_comb" block should not contain any non-blocking assignments | Details |
| VERILOG2116 | Macro concatenation tokens that are not actually concatenating anything should be reviewed | Details |
| VERILOG2117 | Left-to-right streaming operators should not define a slice size | Details |
| VERILOG2118 | In a context where "default_nettype" is set to "none", a net port should not elide its net type | Details |
| VERILOG2119 | Implicit named port connection should not be made between two inequivalent types | Details |
| VERILOG2120 | A "pulsestyle" or "showcancelled" declaration should not target an output terminal that has previously been used in a timing path declaration | Details |
| VERILOG2121 | A constant function should not access a queue with a reversed range | Details |
| VERILOG2122 | "always_ff" block should not contain any blocking assignments for non-local variables | Details |
| VERILOG2125 | Blocking and non-blocking assignments should not be mixed in the same "always" block | Details |
| VERILOG2126 | All conditions should be different within the same "if / else if" conditional statement | Details |
| VERILOG2130 | The type of a case item expression that does not match the type of the case condition expression should be fixed | Details |
| VERILOG2131 | A case item with a known value that makes it impossible to ever match the case condition (or vice versa) should be fixed | Details |
| VERILOG2141 | All paths of a non-void function should return a value | Details |
| VERILOG2142 | A non-void function should return a value | Details |
| VERILOG2143 | A case statement with an enum type condition should cover every enumerand, unless there is a 'default' label | Details |
| VERILOG2145 | Duplicated items in case statement should be removed | Details |
| VERILOG2146 | Overlapping items in case statement should be avoided | Details |
| VERILOG2147 | Unreachable items in case statement should be removed | Details |