Back to Clock Domain Crossings (CDC) Report

clk_reg (rising) => CLK_50MHZ (rising)

Origin Clock Domain	Target Clock Domain	Number of CDCs	Graph
clk_reg (rising)	CLK_50MHZ (rising)	12

CDCs

Summary

ID	Origin Signal	Target Signal
15	`u2_ddr.write_active`	`u2_ddr.data_read`
17	`u2_ddr.write_active`	`u2_ddr.data_read`
19	`u1_plama.u1_cpu.u2_mem_ctrl.address_reg`	`u2_ddr.cycle_count`
20	`u1_plama.opt_cache2.u_cache.state_reg`	`u2_ddr.cycle_count`
21	`u2_ddr.bank_open`	`u2_ddr.cycle_count`
22	`u2_ddr.bank_open`	`u2_ddr.cycle_count`
23	`u2_ddr.bank_open`	`u2_ddr.cycle_count`
24	`u2_ddr.bank_open`	`u2_ddr.cycle_count`
25	`u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg`	`u2_ddr.cycle_count`
26	`u2_ddr.write_prev`	`u2_ddr.cycle_count`
27	`u2_ddr.refresh_cnt`	`u2_ddr.cycle_count`
28	`u2_ddr.state_prev`	`u2_ddr.cycle_count`

CDC #15

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.write_active` Usage: - ddr_ctrl.vhd#223 - ddr_ctrl.vhd#238 - ddr_ctrl.vhd#240	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.data_read` Usage: - ddr_ctrl.vhd#277 - ddr_ctrl.vhd#279	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #17

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.write_active` Usage: - ddr_ctrl.vhd#223 - ddr_ctrl.vhd#238 - ddr_ctrl.vhd#240	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.data_read` Usage: - ddr_ctrl.vhd#277 - ddr_ctrl.vhd#279	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #19

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.address_reg` Usage: - mem_ctrl.vhd#169 - mem_ctrl.vhd#173	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #20

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u1_plama.opt_cache2.u_cache.state_reg` Usage: - cache.vhd#131 - cache.vhd#134 - cache.vhd#135	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > opt_cache2.u_cache (cache) > cache.vhd#130

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #21

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.bank_open` Usage: - ddr_ctrl.vhd#224 - ddr_ctrl.vhd#244 - ddr_ctrl.vhd#249	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #22

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.bank_open` Usage: - ddr_ctrl.vhd#224 - ddr_ctrl.vhd#244 - ddr_ctrl.vhd#249	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #23

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.bank_open` Usage: - ddr_ctrl.vhd#224 - ddr_ctrl.vhd#244 - ddr_ctrl.vhd#249	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #24

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.bank_open` Usage: - ddr_ctrl.vhd#224 - ddr_ctrl.vhd#244 - ddr_ctrl.vhd#249	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #25

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg` Usage: - mem_ctrl.vhd#170 - mem_ctrl.vhd#174	clk_reg (rising)	TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl) > mem_ctrl.vhd#165

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #26

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.write_prev` Usage: - ddr_ctrl.vhd#222 - ddr_ctrl.vhd#232 - ddr_ctrl.vhd#234	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #27

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.refresh_cnt` Usage: - ddr_ctrl.vhd#221 - ddr_ctrl.vhd#253 - ddr_ctrl.vhd#255	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

CDC #28

Origin Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.state_prev` Usage: - ddr_ctrl.vhd#219 - ddr_ctrl.vhd#258	clk_reg (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#218

Target Flip-flop

Graph	Signal	Clock Domain	Flip-flop
	Signal: `u2_ddr.cycle_count` Usage: - ddr_ctrl.vhd#264 - ddr_ctrl.vhd#268 - ddr_ctrl.vhd#269 - ddr_ctrl.vhd#270 - ddr_ctrl.vhd#276 - ddr_ctrl.vhd#278	CLK_50MHZ (rising)	TOP (plasma_3e) > u2_ddr (ddr_ctrl) > ddr_ctrl.vhd#263

Back to Clock Domain Crossings (CDC) Report