HDL1002: The number of clock domains per design should be as low as possible
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| HIGH | - | MEDIUM | Intentionality | Clear | 4h | synthesis, bug-finder, cdc, cnes, clock, cnes-std-04600, linty-ultra |
Description
Keeping the number of clock domains in a design as low as possible limits potential clock domain crossing issues.
An issue is raised if the number of clock domains is greater than the threshold defined through the max
parameter.
Note that a clock domain used for both rising and falling edges is counted as two separate clock domains.
Parameters
| Parameter | Value | Description |
|---|---|---|
| max | 1 | Maximum number of allowed clock domains. Note that a clock domain used for both rising and falling edges is counted as two separate clock domains. |