HDL1010: Output signals should not be constant

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

MEDIUM	-	-	Intentionality \| Complete	30min	synthesis, bug-finder, linty-ultra

Description

Noncompliant code example

entity top is
  port(
    clk : in  std_logic;
    i1  : in  std_logic;
    i2  : in  std_logic;
    o1  : out std_logic; -- Compliant
    o2  : out std_logic -- Noncompliant
  );
end;

architecture rtl of top is
begin
  process(clk) is
  begin
    if rising_edge(clk) then
      o1 <= i1 and i2;
      o2 <= '0'
    end if;
  end process;
end;

Output signal that is a constant might be due to an erroneous or incomplete implementation.

Parameters

Parameter	Value	Description

topPartiallyConstant	true	Set to 'true' to check partially constant output at top level, set to 'false' otherwise