0a06fd02-865f-4c1b-bd39-2a3352bb3f1b

Summary

Count: 1

Clear filters

Rule	Message	Location	Effort	Reliability	Security	Maintainability
HDL1001	Review clock domain crossing between 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (target) and 'u2_ddr.data_read' (origin)	mem_ctrl.vhd#171	0min	HIGH	-	-