0ba16f8b-a193-4610-a781-1c70e76f97fb
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1051 | Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops. | 30min | HIGH | - | - |