1285dfe2-f695-4c84-9601-4495aa9c32a5
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1051 | Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops. | 30min | HIGH | - | - |