214fffdb-3a68-4d59-9dfb-603f2cc50b6a
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1051 | Synchronize the release of asynchronous reset 'u1_plama.u1_cpu.u4_reg_bank.reset_in' into clock domain 'u1_plama.u1_cpu.u4_reg_bank.clk' with at least 2 flip-flops. | 30min | HIGH | - | - |