Linty HDL Designer (HTML Report)
v1.2.3
Summary Report
Design Hierarchy
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VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
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VHDL
Verilog / SystemVerilog
HDL
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VHDL
Verilog / SystemVerilog
HDL
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HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
39106f8d-77be-4523-a4a8-8b59311e359c
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39106f8d-77be-4523-a4a8-8b59311e359c
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HDL1027
Simplify this FSM. Actual number of input signals: 6. Maximum allowed number of input signals: 2.
cache.vhd#43
30min
MEDIUM
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MEDIUM