3e7ff2eb-6157-4844-9b08-81e3897256e5
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u2_ddr.data_write2' (target) and 'u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg' (origin) | 0min | HIGH | - | - |