Linty HDL Designer (HTML Report)
v1.2.3
Summary Report
Design Hierarchy
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VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
Combinational Loops
Latches
Custom Graphs
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VHDL
Verilog / SystemVerilog
HDL
Coding Quality
Measures
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VHDL
Verilog / SystemVerilog
HDL
Accepted Issues
VHDL
Verilog / SystemVerilog
HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
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4b8d7c73-363a-4e62-a40a-1064964fb239
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HDL1027
Simplify this FSM. Actual number of input signals: 10. Maximum allowed number of input signals: 2.
ddr_ctrl.vhd#114
30min
MEDIUM
-
MEDIUM