Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
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Reset Management Module (RMM)
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Unsynchronized Async Reset Release
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VHDL
Verilog / SystemVerilog
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HDL
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VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
508ac826-6716-499a-9548-ed72bf520237
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508ac826-6716-499a-9548-ed72bf520237
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VHDL132
Do not assign this signal that is listed in the process' sensitivity list.
uart.vhd#77
20min
MEDIUM
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