Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
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VHDL
Verilog / SystemVerilog
HDL
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VHDL
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Linty HDL Designer (HTML Report)
v1.2.3
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VHDL1041
Enable signal: pause_in, polarity(ies): active-low
mem_ctrl.vhd#20
0min
-
-
LOW