6a1671fe-d883-4382-8ee1-7692a7111be2
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg' (target) and 'u2_ddr.data_read' (origin) | 0min | HIGH | - | - |