7d9a13a1-74c6-4a8e-b03f-1a97d0529e07
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u1_plama.u2_ram.generic_ram.ram_proc.data' (target) and 'u2_ddr.data_read' (origin) | 0min | HIGH | - | - |