Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
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Linty HDL Designer (HTML Report)
v1.2.3
806f108a-8443-4853-b358-119fa0fb04dd
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806f108a-8443-4853-b358-119fa0fb04dd
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VHDL1046
Remove this non-enable usage of the 'clk' enable signal.
ddr_ctrl.vhd#128
20min
HIGH
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