Linty HDL Designer (HTML Report)
v1.2.3
Summary Report
Design Hierarchy
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VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
Combinational Loops
Latches
Custom Graphs
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VHDL
Verilog / SystemVerilog
HDL
Coding Quality
Measures
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VHDL
Verilog / SystemVerilog
HDL
Accepted Issues
VHDL
Verilog / SystemVerilog
HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
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VHDL1050
Check if this entity can be synthesized with different configurations. If not, remove it.
pipeline.vhd#18
20min
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MEDIUM