Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
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Reset Management Module (RMM)
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Linty HDL Designer (HTML Report)
v1.2.3
916e3ab9-8b7a-4d73-802f-2117777296af
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VHDL1041
This flip-flop defines a complex enable involving 2 signals.
uart.vhd#63
0min
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LOW