Linty HDL Designer (HTML Report)
v1.2.3
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Design Hierarchy
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Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
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VHDL
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Linty HDL Designer (HTML Report)
v1.2.3
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VHDL1041
This flip-flop defines a complex enable involving 1 signal.
reg_bank.vhd#89
0min
-
-
LOW