Linty HDL Designer (HTML Report)
v1.2.3
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
Combinational Loops
Latches
Custom Graphs
Quality Profiles
VHDL
Verilog / SystemVerilog
HDL
Coding Quality
Measures
Opened Issues
VHDL
Verilog / SystemVerilog
HDL
Accepted Issues
VHDL
Verilog / SystemVerilog
HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
c93ef218-5219-4d5b-b3ec-e8e5309e2d9e
View page source
c93ef218-5219-4d5b-b3ec-e8e5309e2d9e
Summary
Count:
1
Clear filters
Rule
Message
Location
Effort
Reliability
Security
Maintainability
VHDL132
Do not assign this signal that is listed in the process' sensitivity list.
uart.vhd#98
20min
MEDIUM
-
-