Linty HDL Designer (HTML Report)
v1.2.3
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Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
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Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Unsynchronized Async Reset Release
Finite State Machines (FSM)
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Verilog / SystemVerilog
HDL
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HDL
False-Positive Issues
VHDL
Verilog / SystemVerilog
HDL
Linty HDL Designer (HTML Report)
v1.2.3
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VHDL185
Update this reserved word to only use lowercase characters.
ram.vhd#146
2min
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LOW