ee29c60c-e87f-440b-a512-fad690495a9f
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1001 | Review clock domain crossing between 'u1_plama.u2_ram.generic_ram.ram_proc.data' (target) and 'u2_ddr.data_read' (origin) | 0min | HIGH | - | - |