ff0348c7-e3a9-40ff-9200-a2e09b28e5a0
Summary
| Rule | Message | Location | Effort | Reliability | Security | Maintainability |
|---|---|---|---|---|---|---|
| HDL1051 | Synchronize the release of asynchronous reset 'u1_plama.reset' into clock domain 'u2_ddr.clk_2x' with at least 2 flip-flops. | 30min | HIGH | - | - |