VERILOG027: “defparam” should not be used
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| - | - | MEDIUM | Consistency | Conventional | 5min | synthesis, vscode, lowrisc, simulation, linter, deprecated |
Description
Articles & blog posts
- lowRISC Verilog Coding Style Guide - Language Features - Module Instantiation
- New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)
- The Art of Deprecation
Noncompliant code example
module fly; defparam my_dream.size = 64; dream my_dream; endmodule : fly
Compliant solution
module fly; dream #(.size(64)) my_dream; endmodule : fly
defparam statement is on the list of deprecation candidates in IEEE 1800-2017 standard (section C.4.1).
The practice of using defparam statements is highly discouraged. Engineers are encouraged to take
advantage of the explicit inline parameter redefinition capability.
Parameter redefinition during instantiation of a module (using the # character) should be used instead.
Moreover, named parameters are recommended.
Parameters
No parameters.