VERILOG029: Each case statement should define a “default” case

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Complete	15min	synthesis, vscode, simulation, lowrisc, linter

Description

Add a default to case statements.

Noncompliant code example

unique casez (select)
  3'b000: operand = accum0 >> 0;
  3'b001: operand = accum0 >> 1;
  3'b010: operand = accum1 >> 0;
  3'b011: operand = accum1 >> 1;
  3'b1??: operand = regfile[select[1:0]];
endcase

Compliant solution

unique casez (select)
  3'b000: operand = accum0 >> 0;
  3'b001: operand = accum0 >> 1;
  3'b010: operand = accum1 >> 0;
  3'b011: operand = accum1 >> 1;
  3'b1??: operand = regfile[select[1:0]];
  default: operand = '0; // Compliant
endcase

Each case statement should define a default case to avoid accidental inference of latches.

Exceptions: unique and priority case.

Articles & blog posts

lowRISC Verilog Coding Style Guide - Language Features - Case Statements

Parameters

No parameters.