VERILOG058: Named port connections should be used for all instantiations

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
MEDIUM	-	MEDIUM	Intentionality | Clear	15min	synthesis, vscode, linter, simulation

Description

Named port connections should be used for all instantiations.

Articles & blog posts

• lowRISC Verilog Coding Style Guide - Language Features - Module Instantiation

Noncompliant code example

fly i_fly (clk_i, rst_ni, from_here, to_there); -- Noncompliant

dream i_dream (abc);

Compliant solution

fly i_fly (
  .clk_i(clk_i),
  .rst_ni(rst_ni),
  .d_i(from_here),
  .q_o(to_there)
);

dream i_dream (abc);

Parameters

No parameters.