VERILOG2020: Vectors should not overflow
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| HIGH | - | - | Intentionality | Logical | 10min | synthesis, vscode, linter, simulation |
Description
Vector overflows lead to unexpected behaviors. Thus, vector overflows should be carefully reviewed.
Noncompliant code example
logic [8:0] i = 7'd256; // Noncompliant: 9 bit needed
Compliant solution
logic [8:0] i = 9'd256;
Parameters
No parameters.