VERILOG2022: An explicit cast should be added to implicit conversion that expands a type
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| LOW | - | - | Intentionality | Logical | 5min | synthesis, vscode, simulation, linter |
Description
Noncompliant code example
logic [1:0] a; int b = a;
Compliant solution
logic [1:0] a; int b = int'(a);
An implicit conversion in an expression expanding a type may be harmless. But the warning provides a mechanism for discovering unintended conversions.
Add an explicit cast if it is intentional to silence the issue.
Parameters
No parameters.