VERILOG2026: Bitwise operators should have operands of same type

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Intentionality \| Logical	10min	synthesis, vscode, linter, simulation

Description

Bitwise operators should have operands of same type. If not, one or both will be converted before the operation is performed. This is not necessarily a problem but the issue can be helpful if you prefer to be strict about disallowing implicit conversions.

Noncompliant code example

module fly;
  logic [7:0] a;
  logic [11:1] b;
  initial a = a | b; // Noncompliant
endmodule

Compliant solution

module fly;
  logic [7:0] a;
  logic [7:0] b;
  initial a = a | b; // Compliant
endmodule

Parameters

No parameters.