VERILOG2041: Bodies of conditional statements and loops should not be left empty
Summary
| Reliability | Security | Maintainability | Code attribute | Effort to fix | Tags |
|---|---|---|---|---|---|
| HIGH | - | - | Intentionality | Complete | 10min | synthesis, vscode, simulation, linter |
Description
A conditional statement or loop with empty body is likely a missing implementation.
Noncompliant code example
module fly;
initial begin
if (1); begin // Noncompliant
end
end
endmodule
Parameters
No parameters.