VERILOG2082: Port direction should be set to “inout” when port is both read and written

Summary

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Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags
-	-	LOW	Intentionality | Clear	5min	synthesis, vscode, linter, simulation

Description

Noncompliant code example

module fly(input wire a, output b);
  assign a = 1;
endmodule

module top;
  wire b;
  fly fly1(1, b);
  assign b = 1;
endmodule

Compliant solution

module fly(inout wire a, inout b);
  assign a = 1;
endmodule

module top;
  wire b;
  wire c = 1:
  fly fly1(c, b);
  assign b = 1;
endmodule

An input net port has been coerced to 'inout' direction because it is assigned to in the instance body. Alternatively, an output net port has been coerced to 'inout' direction because it is assigned externally to the instance. Update direction in source code accordingly.

Parameters

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