VERILOG2083: Implicit conversions in port connection expressions should not expand types

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

LOW	-	-	Intentionality \| Logical	5min	synthesis, vscode, linter, simulation

Description

An implicit conversion in a port connection expression expands a type. This may be harmless, but the warning provides a mechanism for discovering unintended conversions. An explicit cast should be used if it is intended.

Noncompliant code example

module fly(input int a);
endmodule

module top;
  logic [1:0] a;
  fly fly1(.a(a));
endmodule

Compliant solution

module fly(input int a);
endmodule

module top;
  logic [1:0] a;
  fly fly1(.a(int'(a)));
endmodule

Parameters

No parameters.