VERILOG2084: Implicit conversions in port connection expressions should not truncate types

Summary

Reliability	Security	Maintainability	Code attribute	Effort to fix	Tags

HIGH	-	-	Intentionality \| Logical	10min	synthesis, vscode, linter, simulation

Description

Noncompliant code example

module fly(input logic [1:0] a);
endmodule

module top;
  int a;
  fly fly1(.a(a)); // Noncompliant
endmodule

An implicit conversion in a port connection expression truncates a type. This conversion potentially loses data. An explicit cast should be used if it is intended.

Parameters

No parameters.